cystech electronics corp. spec. no. : c912e3 issued date : 2015.07.02 revised date : page no. : 1/8 MTE3D5N06E3 cystek product specification n-channel enhancement mode power mosfet MTE3D5N06E3 features ? simple drive requirement ? fast switching characteristic ? rohs compliant package symbol outline ordering information device package shipping MTE3D5N06E3-0-ub-s to-220 (pb-free lead plating package) 50 pcs/tube, 20 tubes/box, 4 boxes / carton to-220 MTE3D5N06E3 g gate d drain s source bv dss 60v i d @v gs =10v, t c =25 c 80a r dson(typ) @ v gs =10v, i d =30a 3.6m r dson(typ) @ v gs =7v, i d =20a 3.8m g d s environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, ub : 50 pcs / tube, 20 tubes/box product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c912e3 issued date : 2015.07.02 revised date : page no. : 2/8 MTE3D5N06E3 cystek product specification absolute maximum ratings (t c =25c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 60 gate-source voltage v gs 30 v continuous drain current @ t c =25 c(silicon limit) 143 continuous drain current @ t c =100 c(silicon limit) 101 continuous drain current @ t c =25 c(package limit) (note 1) i d 80 pulsed drain current (note 3) i dm 480 continuous drain current @ t a =25 c (note 2) 15.4 continuous drain current @ t a =70 c (note 2) i dsm 12.3 avalanche current (note 3) i as 30 a avalanche energy @ l=100 h, i d =30a, r g =25 (note 2) e as 45 mj t c =25 c (note 1) 188 power dissipation t c =100 c (note 1) p d 94 t a =25 c (note 2) 2 power dissipation t a =70 c (note 2) p dsm 1.3 w operating junction and storage temperature tj, tstg -55~+175 c thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 0.8 thermal resistance, junction-to-ambient, max, (note 2) r th,j-a 62.5 c/w note : 1 . the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and is more useful in setting the upper di ssipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user?s specific board design, and the maximum temperature of 175 c may be used if the pcb allows it. 3 . pulse width limited by junction temperature t j(max) =175 c. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 4 . the static characteristics are obtained using <300 s pulses, duty cycle 0.5% maximum. 5. the r ja is the sum of thermal resistance from junction to case r jc and case to ambient.
cystech electronics corp. spec. no. : c912e3 issued date : 2015.07.02 revised date : page no. : 3/8 MTE3D5N06E3 cystek product specification characteristics (t c =25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 60 - - v gs =0v, i d =250 a v gs(th) 2.0 - 4.0 v v ds = v gs , i d =250 a g fs - 46 - s v ds =5v, i d =20a i gss - - 2 100 na v gs = 2 30v - - 1 v ds =60v, v gs =0v i dss - - 25 a v ds =60v, v gs =0v, tj=125 c - 3.6 4.8 v gs =10v, i d =30a *r ds(on) - 3.8 5.0 m v gs =7v, i d =20a dynamic *qg - 68.3 - *qgs - 11 - *qgd - 28 - nc i d =30a, v ds =30v, v gs =10v *t d(on) - 24 - *tr - 25.2 - *t d(off) - 56.2 - *t f - 17.8 - ns v ds =30v, i d =30a, v gs =10v, r g =1 ciss - 2919 - coss - 585 - crss - 270 - pf v gs =0v, v ds =25v, f=1mhz rg - 1.1 - f=1mhz source-drain diode *i s - - 80 *i sm - - 480 a *v sd - 0.81 1.2 v i s =30a, v gs =0v *trr - 28.7 - ns *qrr - 26.2 - nc i f =30a, v gs =0v, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c912e3 issued date : 2015.07.02 revised date : page no. : 4/8 MTE3D5N06E3 cystek product specification typical characteristics typical output characteristics 0 50 100 150 200 250 300 012345 v ds , drain-source voltage(v) i d , drain current(a) 10v 5v 5.5v v gs =4.5v 6 v 9v 8v 7 v 6.5v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 1 10 100 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =7v 10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 04812162 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c static drain-source on-state resistance vs gate-source voltage 0 10 20 30 40 50 60 70 80 90 100 024681 0 drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =30a v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =30a r ds( on) @tj=25c :3.6m typ
cystech electronics corp. spec. no. : c912e3 issued date : 2015.07.02 revised date : page no. : 5/8 MTE3D5N06E3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss normalizedthreshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) v ds =5v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 0 1020304050607080 total gate charge---qg(nc) v gs , gate-source voltage(v) v ds =30v i d =30a v ds =12v v ds =48v maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 100ms 1ms 100 s r ds( on) limit t c =25c, tj=175, v gs =10v r jc =0.8c/w, single pulse 10 s maximum drain current vs case temperature 0 20 40 60 80 100 120 140 160 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =0.8c/w silicon limit package limit
cystech electronics corp. spec. no. : c912e3 issued date : 2015.07.02 revised date : page no. : 6/8 MTE3D5N06E3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 50 100 150 200 250 300 0246810 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v single pulse maximum power dissipation 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) power (w) t j(max) =175c t c =25c r jc =0.8c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =0.8 c/w
cystech electronics corp. spec. no. : c912e3 issued date : 2015.07.02 revised date : page no. : 7/8 MTE3D5N06E3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c912e3 issued date : 2015.07.02 revised date : page no. : 8/8 MTE3D5N06E3 cystek product specification to-220 dimension *: typical millimeters inches millimeters marking: 4 style: pin 1.gate 2.drain 3.source 4.drain 3-lead to-220 plastic package cystek package code: e3 device name date code 1 2 3 e3d5 n06 inches dim min. max. min. max. dim min. max. min. max. a 4.400 4.600 0.173 0. 181 e 2.540* 0.100* a1 2.250 2.550 0.089 0.100 e1 4.980 5.180 0.196 0.204 b 0.710 0.910 0.028 0.036 f 2.650 2.950 0.104 0.116 b1 1.170 1.370 0.046 0.054 h 7.900 8.100 0.311 0.319 c 0.330 0.650 0.013 0.026 h 0.000 0.300 0.000 0.012 c1 1.200 1.400 0.047 0.055 l 12.900 13.400 0.508 0.528 d 9.910 10.250 0.390 0.404 l1 2.850 3.250 0.112 0.128 e 8.950 9.750 0.352 0.384 v 7/500 ref 0.295 ref e1 12.650 12.950 0.498 0.510 3.400 3.800 0.134 0.150 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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